1. Field of the Invention
This invention relates to a technique for testing semiconductor memory arrays and more particularly to the testing of flip flop memory cells including load devices associated therewith.
2. Description of the Prior Art
Semiconductor memory arrays consisting of flip flop memory cells and fabricated in accordance with integrated semiconductor technology are well known in the art. Hundreds (or even thousands) of these flip flop memory cells may be formed into a single semiconductor chip measuring only a small fraction of a square centimeter in area. Such a semiconductor chip includes a minimum number of accessing terminals or "pads" by which it is electrically connected to other circuit elements in an overall system. Such a dense packing of memory cells with relatively few access terminals raises particular testing problems.
One possible technique for testing memory cells of the type described is to write desired binary information into the cells, pause for a predetermined time, and then read out the information and compare with the information first written into the cells. Such a technique appropriately dubbed the "pause test" is excessively time consuming. Normally, only a small number of the cells on a semiconductor chip can be addressed at any given time during a test in order not to disturb the test status of other cells in the array. Accordingly, the "pause test" must be repeated many times before a particular semiconductor chip is fully tested.
It is also possible to place extra pads on the chip specifically for test purposes. The addition of such pads, however, can decrease the available packing density on the chip and possibly degrade the overall operation of the chip. It is generally considered undesirable to add extra pads (or devices) for merely test purposes. For this reason, the most powerful test techniques are those which require no modification of the product in order to contribute to its testability.